Random access memory (RAM) falls generally into two categories, namely, static and dynamic. Both types of RAM are made up of an array of addressable storage cells, each one storing a bit of information (or multi-bit information). In static RAM (SRAM), the storage unit within the cell is typically a bi-stable flip-flop and the state of the flip-flop indicates whether the cell stores a zero or a one. In dynamic RAM (DRAM) the storage unit is typically an IC capacitor and the charge on the capacitor indicates whether the stored value is either a zero or a one. In the case of DRAM's, however, capacitors gradually lose charge and thus it is necessary to “refresh” the stored data as often as every few milliseconds. The refreshing operation is performed by first reading the value in the cell and then writing it back. This is done for every cell in the array and it typically requires complicated control circuitry.
The earliest DRAM cell, introduced in the early 1970's, contained four transistors. Later, 3-transistor DRAM cells were introduced, which made the cell size smaller and memory density higher. Shortly after, the 1-transistor/1-capacitor cell was introduced, which wiped out all its competitors because of its simplicity as well as its small cell size, and has remained an industry standard. Over the years, through the 4 Kb, 16 Kb, 64 Kb, and 256 Kb SDRAM generation, the cell size was reduced by shrinking both the transistor and the capacitor dimensions. Starting from the 1 Mb SDRAM generation in the mid 1980's, however, the capacitor has been forced to assume a more and more complicated 3-dimensional structure to store enough charges for a given cell size. It is safe to say that the most costly part of the SDRAM cell, including the R&D efforts and the production cost, is, and will continue to be into the foreseeable future, the capacitor. And it may very well discourage continued scaling somewhere down the line, unless a new DRAM cell design is adopted which can live without the capacitor.
Due to its fast switching speed and long retention, FeFET-based memory may be used to perform the functions of DRAM, e.g., as described in U.S. Pat. No. 6,067,244 and/or Non-volatile memory (NVM), e.g., as described in U.S. Pat. No. 5,198,994, each of which are incorporated by reference herein in their entirety.
FeFET-based DRAM (FeDRAM) has several advantages over the conventional DRAM: (1) capacitor-less structure (only one transistor is needed for the memory cell), (2) long retention that enables low refresh frequency, (3) non-destructive “read operation”, (4) small cell size and better scalability, and (5) much more suitable for embedded technology. Use FeDRAM to replace the conventional DRAM has be proposed (see, e.g., U.S. Pat. No. 6,067,244) because the advantages of FeFET-based memory allows FeFET-based memory has faster Program/Erase speed and better endurance than conventional flash memory, making it potentially useful for future storage-class memories. The recent discovery of HfO2-based ferroelectrics (J Müller et al, Appl. Phys. Lett., 99, 112901 (2011)) have overcome the limitations of the state-of-the-art ferroelectric materials, such as Pb(Zr,Ti)O3 (Lead Zirconate Titanate) and SrBi2Ta2O9 (Strontium Bismuth Tantalate), making the FeFET-based 1-transistor (1-T) memory technology more suitable for commercial application.
Special circuits and operation schemes are needed for the operation of FeFET-based memory chips, as they are distinctly different from the circuits designed for other memory technologies.